Sublime Forum

**dkalex** · May 23, 2019, 3:20am

This code work properly.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for type conversions

entity example is
	--generic (
	--	DATA_WIDTH : integer := 8
	--);
	port (
		i_Reset : in  std_logic;
		i_Clock : in  std_logic;
		i_Data  : in  std_logic_vector(DATA_WIDTH -1 downto 0);
		o_Data  : out std_logic_vector(DATA_WIDTH -1 downto 0)
	) ;
end example;

architecture example_arc of example is

begin
	P : process (i_Reset, i_Clock)
	begin
		if (i_Reset = '1') then
			o_Data <= (others => '0');
		elsif (rising_edge(i_Clock)) then
			o_Data <= i_Data;
		end if;
	end process P;
end example_arc;

but this code doen’t

entity example is
	generic (
		DATA_WIDTH : integer := 8
	);
	port (
		i_Reset : in  std_logic;
		i_Clock : in  std_logic;
		i_Data  : in  std_logic_vector(DATA_WIDTH -1 downto 0);
		o_Data  : out std_logic_vector(DATA_WIDTH -1 downto 0)
	) ;
end example;

architecture example_arc of example is

begin
	P : process (i_Reset, i_Clock)
	begin
		if (i_Reset = '1') then
			o_Data <= (others => '0');
		elsif (rising_edge(i_Clock)) then
			o_Data <= i_Data;
		end if;
	end process P;
end example_arc;

**Remi** · May 23, 2019, 12:13pm

Yeah while walking my dog I was pondering this and I think I know what happened, but I’ll have to dig in. While fixing subprogram beautification, there is a problem because interface lists in subprograms can have words like constant and I think I may have put an ignore in there where I shouldn’t. That’s my best guess at the moment. I can probably at least revert that (being able to instantiate the testbench is, in my mind, more important than beautifying subprograms) but we’ll see. Stay tuned.

**Remi** · May 23, 2019, 1:52pm

I have been able to duplicate the issue and I was on the trail, however I had to move onto a different work related problem with a rather nasty git merge. I know where the issue is happening. It is related to the ignores that I put in, but that isn’t strictly the issue, it’s got something to do with the fact that the ignore list is populated but there’s no prior object to compare against when I do the “partial align” that I do when inserting the constants into the testbench. In any event, again, stay tuned, I’ll have this working again as soon as I can. My apologies on this one. I know the testbench creation part of the tool is pretty neat and useful.

Short term workaround, comment out your generics and create the testbench, then manually put the generics in as constants under the signals. That’s what my routine does.

**Remi** · May 24, 2019, 1:13pm

Solved the issue this morning I believe and pushed out a quick fix. Turned out to be my error in checking a deque object with “is not None” and it turns out they’re always present. Suspect I ran into this a long time ago because elsewhere I did correct checks with len(deque_object) > 0 but it’d been awhile since I’ve used it. Anyhow, as soon as Package Control picks up the change you should see this fixed.

**dkalex** · August 3, 2019, 7:14am

Hi Remi
Does your VHDL-Mode Beautify Buffer not support generic type in VHDL 2008?
The result of Beautify Buffer doesn’t looks good.

This is my code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RAM is
	generic (
		RAM_DEPTH : integer := 64;
		type word_type
	);
	port (
		CLK     : in  std_logic;
		RD_ADDR : in  integer range 0 to RAM_DEPTH -1;
		DATA    : in  word_type;
		Q       : out word_type
	) ;
end RAM;

architecture RAM_arc of RAM is
	type mem_t is array (0 to RAM_DEPTH -1) of word_type;
begin
	
end RAM_arc;

and this is the result of Beautify Buffer.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RAM is
	generic (
		RAM_DEPTH : integer := 64;
		type word_type
		);
		port (
			CLK     : in  std_logic;
			RD_ADDR : in  integer range 0 to RAM_DEPTH -1;
			DATA    : in  word_type;
			Q       : out word_type
		) ;
		end RAM;

		architecture RAM_arc of RAM is
			type mem_t is array (0 to RAM_DEPTH -1) of word_type;
		begin

		end RAM_arc;

and sublime text highlight the generic type line like this.
vhdl

**Remi** · August 3, 2019, 1:37pm

It probably does not. I’ll add an issue and get it added! It potentially has a lot of knock on effects though now that I think about it. It’ll hit the syntax – that one is easier. Beautification may be a little harder, but I suspect I’ll just have to make it ignore type when in a generic block (it’s parsing for type, then semi colon – If you reversed the two lines above I suspect you might get different behavior). Interface copying…that one will be interesting.

In any event, I’ll see if I can’t get it added.

**Remi** · August 5, 2019, 2:47pm

This is working up pretty quickly so far. Syntax and beautification were quite simple. Port copying I’m not certain how to accomplish just yet, as it’s setup to treat things in the generic list as constants. If interested in keeping tabs on this, the issue is https://github.com/Remillard/VHDL-Mode/issues/138

**Remi** · August 7, 2019, 1:02pm

Everything seemed to be in order, so I pushed out a release this morning. You should see the generic type support as soon as Package Control picks up the change. You will either need to shut Sublime down and restart, or use the Package Control tool and update the package.

**CrunchyNougat** · June 30, 2020, 4:10pm

Hi Remi,

really nice plugin for an VHDL developer. I am just struggling to use all features of the plugin.
For example the comment M-k c c works properly. But when using the beautify M-k c b nothing happens. Also the testbench M-k p t only opens an empty file. The insert header also does nothing, whether I am using the M-k t h or the right-mouse context menu.

I have a freshly installed sublime-text and added your vhdl-mode plugin.

Do you have any idea what goes wrong?

**Remi** · June 30, 2020, 4:50pm

Well I’m not certain but I can try to make a few suggestions.

First make sure the file type is selected properly. In the lower right hand corner of Sublime Text there should be several fields. The Git branch (if any), Tabe Size, and then the final field is the selected file type. It should read VHDL. If this does not read VHDL, click on the type and it’ll pop open a little menu that lets you select. This most often happens if you have started a new file because Sublime doesn’t know what sort of file it is yet. All the commands are keyed to only operating on VHDL source, so if you don’t have this selected, nothing will work.
Another way to get this done with a new file is to save it immediately. I frequently do a new file from the file selection sidebar, and then with the blank file open, just immediately save it as the source file I intend to write, with the trailing “.vhd” and then Sublime will automatically select VHDL code. Hopefully that will solve the basic things like “insert header”.’
As for the testbench command, it requires that an entity block be copied first. Place the cursor in the middle (it doesn’t need to be exact) of the entity you wish to create a testbench for. Copy the interface ports. If you are curious, VHDL Mode does put out a fair amount of messages so if you hit ctrl- ` you should see the Sublime console and when you copy ports it’ll let you know it found an entity and copied the ports.
Once ports are copied you should be able to create a testbench, and it’ll open a new file, name it, put in the header and fill in a really basic structure with the device under test instantiated.

Hope that helps. I suspect if no commands are working at all it’s because you’re in a blank or misidentified VHDL file. Nearly everything requires source.vhdl scope to operate to make sure it doesn’t get confused trying to do things in a file that is not VHDL.

**CrunchyNougat** · July 1, 2020, 7:19am

Hi Remi,
thank you for your answer!
Sorry I could have been more precise.
In particular, I have tried already different things. The file is saved as .vhd file. I also checked the filetype recognition in sublime text. So it is shown in the lower right corner.
I am working on a Windows 10 machine, if that makes any difference.

Unfortunately, I could not resolve any of the issues yet. Only the commenting works properly.

If I want to add a header, console says: Inserted header template. But the cursor only jumps to the first line of the file. Nothing else happens.

If I run the testbench command, a file is created, and is named correctly like entity_tb.vhd but it is empty.
Console puts out:
vhdl-mode: Interface beginning found.
vhdl-mode: Interface end found.
Traceback (most recent call last):
File “C:\Program Files\Sublime Text 3\sublime_plugin.py”, line 1052, in run_
return self.run()
File “C:\Users\user\AppData\Roaming\Sublime Text 3\Packages\VHDL-Mode\vhdl_interface.py”, line 236, in run
signals_str = _interface.signals()
File “C:\Users\user\AppData\Roaming\Sublime Text 3\Packages\VHDL-Mode\vhdl_lang.py”, line 984, in signals
cb.indent_vhdl(1)
File “C:\Users\user\AppData\Roaming\Sublime Text 3\Packages\VHDL-Mode\vhdl_lang.py”, line 408, in indent_vhdl
rules_str = sublime.load_resource(‘Packages/VHDL Mode/Syntax/beautify_rules.yaml’)
File “C:\Program Files\Sublime Text 3\sublime.py”, line 192, in load_resource
raise IOError(“resource not found”)
OSError: resource not found

Maybe this gives you any hint?

**Remi** · July 1, 2020, 1:33pm

A little bit of a clue, but I have no idea what’s going on. Basically it looks like Sublime is having trouble loading any external resource. The header is actually a snippet that it fills in extra fields so the fact that it’s doing the cursor movement and then doing nothing suggests it didn’t find the snippet to load and insert. The beautification also loads a YAML file resource that has the abbreviated syntax rules I use for beautification.

So while yeah it’s a clue, I have never seen this in 3 years. Congrats!

First, are you having trouble with ANY OTHER plugin? Things like A File Icon and others also load external resources and I’m curious if this is specific to my package or your installation.
After opening Sublime, try looking at the console and scrolling back and seeing if it has any other error messages while loading. I’m wondering if it’s reporting any sort of environmental weirdness.
Did you install Sublime in any non standard fashion? Pretty sure this shouldn’t be an issue, but I don’t honestly know and am really stumped.
Did you install the VHDL Mode package without Package Manager?
Corollary, try going to the packages directory. In Windows this is under C:\Users<username>\AppData\Roaming\Sublime Text 3\Packages. Here you should see VHDL Mode, and then entering that directory you should be able to see a lot of files and Snippets\vhdl-header.sublime-snippet should be present and Syntax\beautify_rules.yaml should be present.
I suppose I should ask what operating system you’re using. Don’t think it’ll matter but good to know. (EDIT: Just saw you mentioned Windows 10, so my path there should be good for you.)
Try uninstalling the package and reinstalling perhaps?

Unfortunately I’ve never had any trouble with Sublime failing to load a resource so either the resource isn’t present or there’s some other file system or operating system issue that’s going on that is preventing them loading the resource. So that’s pretty strange.

Anyhow, hopefully these things will uncover a few clues.

**CrunchyNougat** · July 2, 2020, 8:38am

Hi Remi,
thank you for the feedback and the suggestions. Actually the #4 was the right one.
When I installed vhdl mode I could not find it with the package manager. So I just cloned the github repo into the appdata\roaming\sublime text 3\packages directory.
This made the plugin work partially.
Now, I tried again with the package manager and could install it there as well. Now everything works as expected. Although sublime text handles the package now differently, since it can not be found in the mentioned package directory.

Anyway, thanks for the support. I’ll be using your plugin and report!

**Remi** · July 2, 2020, 2:15pm

Glad that worked for you. It IS possible to get the repo and use it (that’s how I do development) however it doesn’t automatically grab some of the resources necessary (I need the ruamel-yaml library among other things) and it has to be put pretty much EXACTLY where package control would have put it. Also the directory name needs to be exactly “VHDL Mode” (note no dash or underscore like Git likes to use). Anyway, for basic user experience, using Package Control is the preferred method and I don’t have instructions for how to do it from GitHub

Plus, now you have the full range of Package Control packages. You might also want to get the SDF constraints package, and TheClams Verilog/SystemVerilog package as well (it’s good to be fluent in all things HDL – though obviously my personal preferred environment is VHDL)

**CrunchyNougat** · July 7, 2020, 8:16am

It makes definitely more sense to go with the package manager. I usually do it. Except the one case, where I just googled how to use packages from github and I was told just to clone them into the %appdata% folder.
Now, I am aware

I really enjoy the use of the plugin. Makes everything so much easier. Just one question:
I am used to write comments not inline but the line above the code. So it looks like this:

    -- divided clock with 50% duty cycle
    clkDiv : out std_logic;
    -- pulse indicates a rising output clock signal
    clkDivRisePulse : out std_logic;
    -- pulse indicates a falling output clock signal
    clkDivFallPulse : out std_logic;

or

-- set when resync_dir is 10
extend <= '1' when resync_dir = "10" else '0';
-- set when resync_dir is 01
shorten <= '1' when resync_dir = "01" else '0';

In this case the code is not aligned. Would it be possible to use the code align here as well?
Like as long as there is only commented space in between the code lines, they belong together.

**Remi** · July 7, 2020, 12:57pm

Unfortunately no, at least at this time. The problem is that there is no great programmatic way to know when to STOP aligning. That’s been a bit of a pain in the ass since the beginning. The convention I have adopted (and I believe VHDL Mode for Emacs does the same) is that when a different language construct is encountered, then that stops the tracking for the prior alignment group and then performs the alignment. Since you have comments – that counts as a different language construct. Making it ignore comments produces some undesired behavior in other places so comments are not ignored for alignment. I STILL after many years have not 100% solved the problem of the when clause and alignment so very occasionally you may see the => in a when clause align with an (others => '0') if they occur back to back.

I might suggest that you put in a blank line after every comment and code block because that helps the eyeball ignore the fact that the bits are not aligned, and whitespace does help code readability. It signals to the brain that sections are separate and there’s less inherent expectation of alignment happening.

**IMME** · October 10, 2020, 5:27pm

I’m new person who uses Sumlime so I have no idea how to install your package in Sublime.
I’m a little bit frustrated please can you help me?
I just downloaded your files in Github, and there are a bunch of files I would like to know where to move that files…
thank you…

**Remi** · October 10, 2020, 7:12pm

Good afternoon. You probably don’t want to install from Github. Please go to Package Control and install that little script and then you should be able to search for the VHDL Mode plug in and it will install it and the dependencies. If you do it via Github I don’t believe it automatically will install dependencies. Thanks for trying it out! Hope that helps.

**CrunchyNougat** · March 25, 2021, 6:07pm

Hi Remi,

thank you so much for the Update on the VHDL 2008 Syntax. I really love it!

Best wishes,
Sven

**Remi** · March 25, 2021, 6:31pm

You are quite welcome. Wish I had more time to work on it like I did when I started. I use it more than tinker with it (which I guess means it’s pretty stable aside from the occasional blind spot.)

VHDL Mode for Sublime Text 3