I am happy to announce successful publication of my language package for VHDL. The goal was to emulate the vhdl-mode Emacs capabilities and I’ve been able to come close, and work continues.
Major features
- Copying a full port design from an entity or component and instantiating it as entity/component/signal list/instantiation/testbench
- Code beautification (indentation and alignment)
- A mimicry of stutter-typing shortcuts with snippets.
- A set of snippets for language constructs
- Header insertion (somewhat more involved than a snippet)
- A new syntax definition file with fine grained lexical scoping
Thanks to everyone in Plugin Development who put up with my running commentary and questions. You all deserve massive credit for making the development process successful.
If anyone actually is simultaneously a hardware developer, Sublime Text user, and VHDL coder I hope this helps you out.
(Actually I guess it’s not yet completely merged into Package Control channel, so might not be on the website just yet.)