Hi
I’m back again 
Maybe i’m stiil make a mistake, but i noticed a strange behavior in syntax highlighting.
I have a module called if_cpu. And in another module, i want to instanciate this module. So i wrote:
i_if_cpu : if_cpu
port map (
[...]
);But, starting to the instanciation line, my code is no more highlighted. It seems that name ‘if_cpu’ is considered as a “if” statement. I’m telling that, because if the module is named “mif_cpu” then there is no more syntax highlighting issue.
Yep that’d be an honest to god bug. I’ll add that to the issues list on GitHub. Thanks!
(Though seems to me like if shouldn’t have context in a location where you can instantiate things. If is a sequential style statement, and instantiations are concurrent. It’s still a bug, just might not be where I thought it was originally.)
If you ever are curious about a syntax issue, the best tool is using the scope. There’s a way to do it in ST3, Tools >> Developer >> Show Scope Name. I also have a utility in the package that prints the scope to console Alt-k S.
It looks like this is a bug that came into being when I was adding the conditional generate stuff which DOES put if statements into concurrents. It may be as simple as making sure the if has whitespace boundaries around it.
Easy to fix. Should be there as soon as Package Control picks up the release and you restart ST.
Hi,
Guess who is back again ?
I’m still using your plugin, and for now it is answered for about 90% on my needs. The 10% less are about some specific functions that i used to use in other editor, and much of them are links to ST3 missing features.
However, i’ve a question. And maybe, you 'll tell me that this is a ST3 feature and/or issue.
It is possible in the VHDL mode to have “smart indent”. Let me explain myself:
If i wrote an “if” branch with or without the snippet, for example:
if ( a > 1 ) then
b <= x"0";
end if;But if i want to add an “else” branch, i go to line “b <= x"0"” then i press enter. What i want is that the cursor goes to the same level than the if (means backward of 2 spaces (2 is my indent value)), and so after write “else” and press “enter” the cursor goes to next line and add 2 spaces of indentation.
I hope i was clear in my description.
This is possible via some extra indentation metadata that the package is not currently providing. I’ll leave it up to @Remi as the VHDL master to fully determine the rules needed and how they should look, but trivially speaking if you create a file with the following contents and store it in your User package with a name like Indentation.tmPreferences (only the extension is important), you can get up and running for some testing. You can use Preferences > Browse Packages... to find your User package if you don’t know where it is.
<?xml version="1.0" encoding="UTF-8"?>
<plist version="1.0">
<dict>
<key>name</key>
<string>Indentation Rules</string>
<key>scope</key>
<string>source.vhdl</string>
<key>settings</key>
<dict>
<key>decreaseIndentPattern</key>
<string>(?x)
^ \s* else \s* $
</string>
<key>bracketIndentNextLinePattern</key>
<string>(?x)
^ \s* else \s* $
</string>
</dict>
</dict>
</plist>
In short this says that the word else alone on a line should be unindented, but the line following the word else on it’s own line should be indented.
In use, when you press Enter the new line will still be indented, but as soon as you finish typing else it will automatically unindent the line that the else is on, and when you press enter the indent will jump back up to the appropriate level again.
Note: If you do this, you want to remember to remove the file if/when the VHDL package gets its own version to make sure that everything works as expected.
More information on how the indent system works is available here:
I have looked into automatic indentation, experimented with it a bit, however never found a set of settings that to me felt natural. I can try looking into it again, but I’ve got several other issues that will take priority (and I’m behind on those already as well due to non-package obligations.)
So, in short, it’s possible, but not currently supported by my package. If someone wants to submit something that they feel works well for this, I’m open to contributions for the package.
Hi Remi,
Great stuff!
I’ve an idea for possible extra feature for “Code Beautify” which would make VHDL mode even better.
Pic bellow shows Case1 & 2 where CB would make code less to my opinion less readable. I understand those cases would probably require a lot of smart logic to recognize correct indentation, so would there be an easy way to locally disable CB, just with some tags --CB_OFF / --CB_ON?
Many thanks for your reply.
Kind regards
Hmm. Beautification pragmas. It might be doable though I’ve just got through a really big refactor on the beautification design where I wholly remove comments from any indentation consideration. I’ll have to think about it to see how it might be improved.
For your case 1 I might suggest the following style that preserves your intent and readability:
identifier <=
concat1 &
concat2 &
concat3;
This will preserve your alignment at the expense of one carriage return. I’ve thought about trying to align multiline assignments after the operator, but the prior beautification method would only indent due to an incomplete statement. There might be a way to do a second pass looking for such a construct but I also worry that the more specific task passes I put in there, the slower beautification will get.
On your case 2, it might be possible to put in an alignment for the & character however even that wouldn’t solve your issue because my alignment routine doesn’t perform multiple scans per line for a character; it just aligns the first one it finds. And in fact, I’m not sure there’s a nice automated way to know the intent of the engineer here. One of the trickiest things I’ve found with beautification is trying to come up with rules that work for a variety of coding styles. They’ve got to work for not only the bulk of code, but not cause any trouble in edge cases, so I’ve kept things somewhat simplified.
So we’re back to pragmas, but that has its own issues as noted because I mask off comments before evaluating lines for indentation. Getting a regular expression to trigger is easy. Getting it to only trigger in the right circumstance is decidedly harder.
In any event, I’ll take it under consideration and add an issue for it for tracking until I decide I can (or will) do something about it, or won’t. Right now I’m trying to knock out as many issues for a 1.8.0 release as I can, and then eat my own code for awhile.
Hi Remi,
I am new to Sublime Text 3.
I have found a defect in the Beautify Buffer command of the VHDL Mode.
If VHDL comments are written as such:
entity test
port(
myport1 : in std_logic; -- this port associated with : test 1
myport2: out std_logic; -- this port is associated with : test 2
myport3 : out std_logic -- this port was associated with : test 3, but is now unused, leave open in port map
);
end entity test;
The Beautify Buffer command will inserted seemingly random whitespace on either side of the ‘:’ character within the comment text on the right side of the comment token ‘–’ . I would like to ask if you can fix this to not change preformatted text on the right side or the comment token ‘–’.
Well I’m having trouble replicating exactly what you’re talking about here. If I put in the text you display above, and then beautify, I get the following:
entity test
port(
myport1 : in std_logic; -- this port associated with : test 1
myport2 : out std_logic; -- this port is associated with : test 2
myport3 : out std_logic -- this port was associated with : test 3, but is now unused, leave open in port map
);
end entity test;
I see no additional space around the : in the inline comment. I tried another case where I altered your example to really remove all space around ::
entity test
port(
myport1 : in std_logic; -- this port associated with:test 1
myport2: out std_logic; -- this port is associated with:test 2
myport3 : out std_logic -- this port was associated with:test 3, but is now unused, leave open in port map
);
end entity test;
Running beautify against this produces:
entity test
port(
myport1 : in std_logic; -- this port associated with:test 1
myport2 : out std_logic; -- this port is associated with:test 2
myport3 : out std_logic -- this port was associated with:test 3, but is now unused, leave open in port map
);
end entity test;
Note that the spacing around : is preserved.
However all that being said, this was tested with version 1.8.0. This is actually relatively newly released and due to the Package Control incident last week and weekend, it’s possible that you are not running this version and I think the prior version of the package was less careful about comments. So if you could check what version you’re running it’d be helpful.
You can always find out what version you’re running by using the Command Palette and selecting VHDL Mode - Version (Console) or by using the keybind for it Alt-k V. Be sure to have the console open with `Ctrl-`` . If you’re not running 1.8.0 you can make the Package Control package update this by going to the Command Palette and going to Package Control: Upgrade Package and it ought to refresh its knowledge of latest versions and see if there’s not an update for VHDL Mode available.
So, give that a shot and let me know what happens. One of the big tasks for 1.8.0 was to refactor the beautification routine so that I had the opportunity to do smarter things with comments, both full line and in-line comments like you see here. If that doesn’t solve your problem, let’s see if we can come up with a test case that demonstrates exactly what you’re looking for.
Hi, I am new to Sublime Text.
Thank you for your job, but I have some issues using your package. I installed Sublime Text 3 build 3200 and VHDL Mode v.1.8.2. Code highlighting and snippets are working fine, but others functions aren’t. I can’t use extended commands and stutter typing, nothing happens. At the same time I can go to VHDL Mode settings via ST menu, and no errors occur.
Maybe there is some option to activate all functions and I just can’t find it?
Thank you.
Thanks for trying it out. Since the package has worked for some time now, I have to suspect there’s just something simple that’s going on. The keybinds and commands are context sensitive. If you are not in a file with syntax selected for VHDL then the commands won’t work.
That said, presumably you’re in a file like that if you’re seeing syntax coloring and snippets which are ALSO context selective for that language. Perhaps you can give me a sequence of events that reproduces what you’re seeing and we can try to figure out where the issue is.
The problem was solved when I installed VHDL Mode from package control. Now all functions work fine.
Hey great! I hope it works out well for you. There are some bugs that are on my TODO list, but work’s been absolutely insane the past month while we bring up this new design, so I’ve just been making a backlog of things to fix.
Paste as Testbench doen’t work when entity includes generic.
Sublime Text 3 console shows this
after “Copy Ports”
vhdl-mode: Interface beginning found.
vhdl-mode: Interface end found.
after “Paste as Testbench”
Traceback (most recent call last):
File “C:\Sublime Text Build 3207 x64\sublime_plugin.py”, line 1052, in run_
return self.run()
File “C:\Sublime Text Build 3207 x64\Data\Installed Packages\VHDL Mode.sublime-package\vhdl_interface.py”, line 200, in run
File “C:\Sublime Text Build 3207 x64\Data\Installed Packages\VHDL Mode.sublime-package\vhdl_lang.py”, line 967, in constants
File “C:\Sublime Text Build 3207 x64\Data\Installed Packages\VHDL Mode.sublime-package\vhdl_lang.py”, line 444, in indent_vhdl
IndexError: deque index out of range
Thanks for letting me know. I may have borked something because it should have made constants for the generics. I’ll take a look at it in the morning. It may be helpful if you could post the offending code (or a minimal functional demonstrative example) but I"ll try some stuff and see what pops out.
This code work properly.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for type conversions
entity example is
--generic (
-- DATA_WIDTH : integer := 8
--);
port (
i_Reset : in std_logic;
i_Clock : in std_logic;
i_Data : in std_logic_vector(DATA_WIDTH -1 downto 0);
o_Data : out std_logic_vector(DATA_WIDTH -1 downto 0)
) ;
end example;
architecture example_arc of example is
begin
P : process (i_Reset, i_Clock)
begin
if (i_Reset = '1') then
o_Data <= (others => '0');
elsif (rising_edge(i_Clock)) then
o_Data <= i_Data;
end if;
end process P;
end example_arc;
but this code doen’t
entity example is
generic (
DATA_WIDTH : integer := 8
);
port (
i_Reset : in std_logic;
i_Clock : in std_logic;
i_Data : in std_logic_vector(DATA_WIDTH -1 downto 0);
o_Data : out std_logic_vector(DATA_WIDTH -1 downto 0)
) ;
end example;
architecture example_arc of example is
begin
P : process (i_Reset, i_Clock)
begin
if (i_Reset = '1') then
o_Data <= (others => '0');
elsif (rising_edge(i_Clock)) then
o_Data <= i_Data;
end if;
end process P;
end example_arc;Yeah while walking my dog I was pondering this and I think I know what happened, but I’ll have to dig in. While fixing subprogram beautification, there is a problem because interface lists in subprograms can have words like constant and I think I may have put an ignore in there where I shouldn’t. That’s my best guess at the moment. I can probably at least revert that (being able to instantiate the testbench is, in my mind, more important than beautifying subprograms) but we’ll see. Stay tuned.
I have been able to duplicate the issue and I was on the trail, however I had to move onto a different work related problem with a rather nasty git merge. I know where the issue is happening. It is related to the ignores that I put in, but that isn’t strictly the issue, it’s got something to do with the fact that the ignore list is populated but there’s no prior object to compare against when I do the “partial align” that I do when inserting the constants into the testbench. In any event, again, stay tuned, I’ll have this working again as soon as I can. My apologies on this one. I know the testbench creation part of the tool is pretty neat and useful.
Short term workaround, comment out your generics and create the testbench, then manually put the generics in as constants under the signals. That’s what my routine does.