Hello,
Let’s say the ports of the SystemVerilog module have been changed (port names, widths, etc).
How to update the ports in the instance of the module as well?
How to update the ports in ALL the instances of the module in the Project?
Thank you!
[SystemVerilog PlugIn] How to update instance ports?
Clams
#2
It is not supported: you can just recall the instance function to update the port name, but any type change will be ignored.
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ldm_home
#3
so, if I changed the names of the signals, which are connected to the ports, will they be lost?
By default, the instance ports are connected to the same signals as the port names. But if I changed the names of connected to the ports wires and then recall to the instance function again, will all my changes lost? Is there a way to keep the connected wires and update just the instance port list? Are there another solutions/walk arounds?
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ldm_home
#4
Is it possible to write some macro/python, which goes over all the ports of the instance and remove the ports, which are not already present in the module or adds new ports, which were added to the module since it was instantiated?
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