Hi All,
By default the Verilog/SystemVerilog instances are declared without parameters.
For example, there is a following module:
`module M #(parameter P) (input A, output B)
So, the default instance, which is triggered by the verilog_module_inst command, will be like following:
M i_M (.A,(A).B(B));
But, how to get the instance of the module with its parameters like following?
M i_M #(.P(P)) (.A(A), .B(B));
Thank you!
`
Thank you!
If you open preferences -> packages settings -> SystemVerilog -> Settings, you can set sv.param_explicit to true: in this case the parameter should appear even when default value is used.
Thank you a lot for your answer, but:
Where should I do the change - in the default or user settings?
I tried to do this change in the default settings, but they are read-only.
I tried to add the definition to the User Settings, but received the following error message:
So where to add the sv.param_explicit definition and how?
Thank you!
All sublime-settings files should have a { as the first character in the file and a } as the last character, so adding that should fix it.
They’re required in all settings files, but sometimes when packages set up the menu entries for creating their own settings they don’t include the { } in the template content that gets added when the file doesn’t exist yet. So occasionally when configuring a package for the first time you might need to add them in yourself.
