System verilog beautify

[yoti]

Hi
is there a system verilog beautify package?
thanks
yoti

[Clams]

There is a beautify feature in the system verilog package. It is far from perfect and still a work in progress, but it is better than nothing

[Remi]

If it is of any benefit, I think my beautify engine for VHDL is working decently and it’s language agnostic to some degree. It might be adaptable, but I just don’t know SystemVerilog well enough to know where the pitfalls might be and I don’t have a wide base of examples to draw upon.

In any event, there might be some potential there.if interested.

[yoti]

how do i use it?

[Clams]

Select the lines you want to align and open the command palette (ctrl+shift+p) and select Verilog: Align.
The readme of the plugin gives instruction for keybinding if needed.