Syntax Highlighting for Verilog, SystemVerilog and UVM

[piyushkamalakar]

I was wondering if there is any syntax highlighting feature for Verilog, SystemVerilog and UVM on Sublime Text 3.

[rwols]

https://packagecontrol.io/packages/SystemVerilog

[Fynjisx]

Qt has such a feature in the ifdef … endif blocks if the macro is not defined, then it is shaded in the conditional block. Why not implement it here?

[deathaxe]

This request is off topic!

[Fynjisx]

Well, where to ask this question? This category is “Wishes and Suggestions”!

[jfcherng]

Well, where to ask this question? This category is “Wishes and Suggestions”!

Create your own thread. No one is discussing Qt in this thread, or if you read the thread title.