[Snippets] What's scope for SystemVerilog files?

[ldm_home]

Hi All,

While creation the snippets, there is a need to define scope - what file types would recognize the snippets.

How should I define a scope for the Verilog/SystemVerilog files?

I’ve tried the following, no one of them worked:

<scope>.v</scope>
<scope>*.v</scope>
<scope>.sv</scope>

Please advice.

Thank you!

[jfcherng]

ctrl+alt+shift+p should show the full scope at the cursor position. The top (base) scope should usually be source.xxx or text.xxx.

[Remi]

At least with the SystemVerilog package by TheClams, the scope is simply source.systemverilog