Match if endif in VHDL

[acheriti]

Hi,
I’m currently using ST for coding some VHDL and I was wondering is there a setting I could add to easily see the if/endif matching just like the package bracket highlighter work for general C?
Thank you!

//**//
if (rising_edge(CLK)) then
if (ARESET =‘1’) then

else
  if (rise) then

    if (count length)
      then valid   <= '1';
           
      else valid   <= '0'; 
    
    end if;
    --
    mem <='1';
  end if;
end if;

end if;

[jfcherng]

I did that for Verilog before.

The problem is the else. I couldn’t find a way to make it work with

• if/else
• else/endif
• if/endif (if there is no else)

instead, I did only

• if/endif