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How to run verilog code in sublime text 3

#1

Hi All,
I am a newbie and want to run verilog codes in sublime text 3.can anyone of you guide me regarding the process and if there is any build system script for verilog then please do share.

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#2

There are several Verilog packages on Package Control. I use https://packagecontrol.io/packages/SystemVerilog

There is not a default Verilog build, however I use the following in my project files. You’ll have to edit to make it work for you. It goes under “build systems”. This is for Riviera-PRO simulation:

		{
			"file_regex": "^COMP96 File: (.*)",
			"line_regex": "^COMP96 ERROR (?=\\w*: \\\".*\\\" (\\d*) (\\d*))(\\w*: \\\".*?\\.\\\")",
			"name": "Riviera PRO SystemVerilog",
			"selector": "source.systemverilog",
			"shell_cmd": "vlog -dbg +accb +accr +accs +dacc -dpilib -protect 0 -time -sve -multiplatform -work work $file",
			"working_dir": "$project_path/simulation"
		},

Please note you’re talking about an HDL. It’s not your normal procedural language. You’ll need a simulator and such to handle it.

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