hello, I am new to build systems. I have it set up correctly and it builds all ok. Now I want to show only the important part on my console output. An example output is as below:
VHDL/Verilog/EDIF/SystemC Simulator build 10.3.3558.6081
(c) 1997-2016 Aldec, Inc. All rights reserved.
License Number 0
Welcome to VSIMSA!
This message was printed from `startup.do' macro file.
# creating library
alib work
ALIB: Library `work' attached.
Compile success 0 Errors 0 Warnings Analysis time : 31.0 [ms]
Compile Package "BT601_cfg"
Compile success 0 Errors 0 Warnings Analysis time : 15.0 [ms]
# starting simulation with tb_top as the top level module
# asim fpc_tb
# running the simulation
# run 1000us
echo hi
hi
quit
To get started I want to pick these lines:
Compile success 0 Errors 0 Warnings Analysis time : 15.0 [ms]
my regex is as follows:
^Compile success [0-9]+ Errors [0-9]+ Warnings Analysis time : [0-9]+.[0-9]+ [ms]
how can I use this in my “file_regex”: “” ?
thank you