Sublime Forum

The most flexible alignment tool: AlignTab

#21

I’m using ST3 buld 3056 - Windows 7 x32

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#22

do you still have problem with exiting the table mode?

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#23

I tested in ST3 on Windows 8 64bit and it doesn’t seem do have any problems.

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#24

using it in CSS, is there a way to add “{” as an align mode, in the right click interface?
adding it to the settings file does not seem to affect it.

(except regexp)

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#25

[quote=“sneila”]using it in CSS, is there a way to add “{” as an align mode, in the right click interface?
adding it to the settings file does not seem to affect it.

(except regexp)[/quote]

you can create your own Context.sublime-menu and put it under User.

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#26

So f*****g sexy. Imagine the possibilities!

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#27

Hey all. I don’t know much about regex, but this tool looks like it would be perfect for aligning verilog port lists. Could anyone help me figure out how to configure it to turn code like this:

input [17:0] SW, // write enable, write address, input data input [0:0] KEY, // reset input CLOCK_50, // 50 MHz clock output [0:0] LEDG, // write enable output [0:6] HEX7, // write address output [0:6] HEX6, // write address output [0:6] HEX5, // data in output [0:6] HEX4, // data in output [0:6] HEX3, // read address output [0:6] HEX2, // read address output [0:6] HEX1, // data output output [0:6] HEX0, // data output output [17:0] LEDR // switches
into code like this:

input [17:0] SW , // write enable, write address, input data input [0 :0] KEY , // reset input CLOCK_50, // 50 MHz clock output [0 :0] LEDG , // write enable output [0 :6] HEX7 , // write address output [0 :6] HEX6 , // write address output [0 :6] HEX5 , // data in output [0 :6] HEX4 , // data in output [0 :6] HEX3 , // read address output [0 :6] HEX2 , // read address output [0 :6] HEX1 , // data output output [0 :6] HEX0 , // data output output [17:0] LEDR // switches
Thanks.

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#28

it is hard to align table with missing values. My suggestion is to use

\s*

and then edit the table manually for the missing cells.

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#29

Hi,
First of all, thank your for the plugin it is very usefull.

However, i have a question:
I want to align the following case:

signal sig1 : std_logic := 0;
signal sig2 : std_logic_vector( 3 downto 0 ) := x"4";
signal sig_out : std_logic := 1;

If i use the plugin to align lines according to ‘:’, ia have a wrong behavior. The result is

signal sig1    : std_logic                      : = 0;
signal sig2    : std_logic_vector( 3 downto 0 ) : = x"4";
signal sig_out : std_logic                      : = 1;

The problem is that plugin align lines according to ‘:’ but also according to ‘:=’ which i don’t want. Moreover, character ‘:’ is not equivalent to ‘:=’ so why plugin make this alignment ?
Thanks

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#30

In your case the function First Colon : in the AlignTab context menu item would solve the problem.

You can also run AlignTab from Command Palette and enter the regexp :(?!=)

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#31

Ok, i’ve missed the operation available in the context menu.
Thanks.

I’ve another problem. For example i’ve the following code (language is VHDL but whatever):

p_release: process(nRst, ClkSys)
begin
   if (nRst = '0') then
      toto                <= (others=>'0');
   elsif rising_edge(ClkSys) then
      if (cs_controlReg = '1') and (wr_en = c_WE_active) then
         if Addr(5 downto 0) = c_addr(7 downto 2) then
            toto(0)   <= Data_in( 0);
            toto(1)   <= Data_in(16);
         else
            toto      <= (others => '0');
         end if;
      else
         toto        <= (others => '0');
      end if;
   end if;
end process;

As you can see, there is many indentation level. But if i want to align all symbol “<=”, it will work but the indentation will be broken:

p_release: process(nRst, ClkSys)
begin
   if (nRst = '0') then
      toto    <= (others=>'0');
   elsif rising_edge(ClkSys) then
      if (cs_controlReg = '1') and (wr_en = c_WE_active) then
         if Addr(5 downto 0) = c_addr(7 downto 2) then
      toto(0) <= Data_in( 0);
      toto(1) <= Data_in(16);
         else
      toto    <= (others => '0');
         end if;
      else
      toto    <= (others => '0');
      end if;
   end if;
end process;

Did i made a wrong operation or is it a real plugin issue?

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#32

I guess something like that was already reported. Maybe upvoting it?

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#33

(Experimental) Besides r, c and l, there is a new u flag which stands for “unjustified”.

If the first indent of the line is correct, you can use something like:
<=/ur

p_release: process(nRst, ClkSys)
begin
   if (nRst = '0') then
      toto          <= (others=>'0');
   elsif rising_edge(ClkSys) then
      if (cs_controlReg = '1') and (wr_en = c_WE_active) then
         if Addr(5 downto 0) = c_addr(7 downto 2) then
            toto(0) <= Data_in( 0);
            toto(1) <= Data_in(16);
         else
            toto    <= (others => '0');
         end if;
      else
         toto       <= (others => '0');
      end if;
   end if;
end process;
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#34

Well it’s work.
Is it possible to have this behvior by default ?
Because it will be easyier to not add this flag each time i want to use the plugin ?

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#35

No because this is a flag that is applied to one column, not a global flag.

But you can create some predefined function in either context menu, command palette or keybinding.

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#36

Thanks for the tips.
It works fine.

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