[quote=“mpr90”]Very nice plugin; I’m using it daily. I wasn’t aware of the alignment feature, and have been using the excellent AlignTab plugin, but will look at your alignment features too.
Thanks![/quote]
Check all features in the documentation with video examples sv-doc.readthedocs.org/en/latest/
Anyone having issues with the reindent with lines that are just comments?
Can you post an example of your problem ?
Edit: The best way is to post your issue (code example+description of what you expect and what really happen) on the github repo, this way I will get a notification 
Hello!
Thank you for the plugin, it is very useful for my work
But what about coding style - how to change it:
for example
always_ff @(posedge clk) begin : bla
end
I want to change to:
always_ff@(posedge clk)
begin : bla
end
Is any possibility of such trick exist?
Have you tried setting sv.indent_style to gnu ? Or you also don’t want indentation for the begin keyword ?
I’m still maintaining this plugin and I had some fun with the use of phantoms to provide a nice side-bar to explore hierarchy (class/module), so I though I would share it here, it could maybe inspire other plugin developers:
That’s pretty cool. I was working towards a “speedbar”-like hierarchical display, to the point of having a method to map out an entire directory’s contents of modules/entities/instantiations but then I got stuck with the actual implementation in Sublime.
Are you using Sublime’s object detection here, or do you have something that scans and caches files and locations throughout?
And actually would it be worth spinning this out into a separate HDL outliner package? I would be more than happy to contribute on the VHDL side of the world (my Verilog-fu is meh. I get by but I’m not an expert.)
I’m using a mix of Sublime’s symbol indexing and some manual parsing of file for a few stuff (like module ports).
The fact that I display sub-level only on-demand allows to keep things simple, I basically juste need to parse manually one file, so no need to cache, and since i’m looking only for a limited amount of stuff it’s easy to do with regexp.
Since I rely on sublime’s indexing, it might not be really clean to have this in a separate package from the syntax, but on the other hand it could allow a multi-language side-bar which would actually be great.
Okay. Yeah if it’s just within a single file, that’s far easier to do with Sublime’s symbol tools. My script basically indexed an entire tree with file and position. I had a lot of trouble with regex for Verilog instantiations because really gargantuan instantiations would cause catastrophic backtracking. I ended up having to strip out parenthesis interiors which ended up making the regex’s faster even though it’s a hack.
However it did scan an entire project directory tree with mixed Verilog, SystemVerilog (these were mainly IP from Quartus regarding the processor system) and VHDL and created a tree in about 4 seconds – smaller projects are pretty much instantaneous – so even if a hack I was generally pleased with it.
I just couldn’t figure out what to do with it AFTERWARDS because I got very fixated on using the sidebar as an outline. I guess you must keep a mapping in your panel between cursor location and file location. Also folding was very frustrating to work with in Sublime. I don’t remember exactly what the issue was, maybe it was the inability to mark code spots for folding rather than basing it all on indentation.
Unfortunately, we’re getting phase 2 of our boards in … probably T minus 20 minutes now and all hell is going to break loose at that point. I’m going on vacation next week so I’ll probably have some time to browse your repository and see how you do your panel mapping.
If my stuff is at all interesting, I have it stashed in https://github.com/Remillard/HDL-Outliner/blob/develop/hdl_outline.py. I’d started that project but it’s been dormant for awhile as I was out of ideas and time at the time. There’s a sample project output of this big project in the test directory in that same git project. I was styling it like Emacs Speedbar, but that only ever indexed VHDL and mine does everything I think.
