Okay. Yeah if itās just within a single file, thatās far easier to do with Sublimeās symbol tools. My script basically indexed an entire tree with file and position. I had a lot of trouble with regex for Verilog instantiations because really gargantuan instantiations would cause catastrophic backtracking. I ended up having to strip out parenthesis interiors which ended up making the regexās faster even though itās a hack.
However it did scan an entire project directory tree with mixed Verilog, SystemVerilog (these were mainly IP from Quartus regarding the processor system) and VHDL and created a tree in about 4 seconds ā smaller projects are pretty much instantaneous ā so even if a hack I was generally pleased with it.
I just couldnāt figure out what to do with it AFTERWARDS because I got very fixated on using the sidebar as an outline. I guess you must keep a mapping in your panel between cursor location and file location. Also folding was very frustrating to work with in Sublime. I donāt remember exactly what the issue was, maybe it was the inability to mark code spots for folding rather than basing it all on indentation.
Unfortunately, weāre getting phase 2 of our boards in ā¦ probably T minus 20 minutes now and all hell is going to break loose at that point. Iām going on vacation next week so Iāll probably have some time to browse your repository and see how you do your panel mapping.
If my stuff is at all interesting, I have it stashed in https://github.com/Remillard/HDL-Outliner/blob/develop/hdl_outline.py. Iād started that project but itās been dormant for awhile as I was out of ideas and time at the time. Thereās a sample project output of this big project in the test directory in that same git project. I was styling it like Emacs Speedbar, but that only ever indexed VHDL and mine does everything I think.